From NanoMEGAS
The Challenge:
Characterise Copper Interconnect lines (CI) grain boundaries and texture at 1 nm scale
The Solution:
ASTAR technique couple with precession electron diffraction
The scaling required to reach faster chip performances in electronic devices has pushed the dimensions of copper interconnect (CI) lines to the nanometer domain. This constant downscaling of CIs implies a change in their microstructure. A change in the grain boundary type distribution and local texture will strongly influence the resistivity and the mechanical reliability of downscaled CIs. A different texture can imply different mechanical properties and a different local distribution of stresses. It is, therefore, necessary to map the texture evolution with the size of CIs. READ MORE IN THE ARTICLE BELOW.
ADVANCED IMAGING AND DIFFRACTION TOOLS FOR TRANSMISSION ELECTRON MICROSCOPY
Faster chip performances in ever shrinking electronic devices push circuits down to nanometer size. Spintronic devices and optical properties of organic semiconductors depend on their nm level local structure . Orientation and phase mapping with ASTAR sheds light to local texture and phases, while 3D electron diffraction tomography reveals detailed crystal structure of possible impurities. As metrology tool detailed strain maps down to nm scale allow to monitor precisely electrical properties and avoid device failure.
Intrigued?
To talk about your application, get in touch with our Technical Director, Dr. Shayz Ikram by email below or call (01372) 378822.
